Information

There has been much written about the use of processor models to assist in the development of software. Back in the 1970′s the early versions of Unix on a PDP11 included a simulator of the Motorola 6800 – one of the first Instruction Set Simulators made readily available. It ran very slowly and its focus was to explore the details of the instructions. Today processor models and simulators can have various usage targets.

The models listed on this site are all available from OVP and are written to be Instruction Accurate and are targeting the development of embedded software. Please search elsewhere for models to be used to test pipelines, cache behaviors, branch predictors and other aspects related to low level performance or power analysis of cpu architectures.

These Information pages list some of the relevant companies, organizations, and players in the CPU modeling and Virtual Platforms ecosystem.

The Information menu provides access to several pages of information:

The page information/using-fast-cpu-models-in-c-platforms/  provides information and links about how to use the OVP Fast Processor Models in C Platforms.

The page information/using-systemc-tlm2-processor-models/  provides information and links about how to use the OVP Fast Processor Models in SystemC with TLM2.

The page cpu-model-emulator.com/information/downloading-the-models/ introduces how to get the models and install/use them.

The links page provides links and information on the Fast CPU Models and Virtual Platform ecosystem..

There is also a glossary page and a news page.

If you feel more and different information would be useful – please let Imperas know at info@imperas.com.


Currently available Fast Processor Model Families.

FamilyModel Variant
Renesas Models    Renesas Models aliases V850 V850E1 V850E1F V850ES V850E2 V850E2M V850E2R RH850G3M m16c r8c RL78-S1 RL78-S2 RL78-S3 (aliases)
RISC-V Models    RISC-V Models aliases RV32I RV32IM RV32IMC RV32IMAC RV32G RV64I RV64IM RV64IMC RV64IMAC RV64G RISCV_UISA (aliases)
MIPS Models    MIPS Models aliases ISA M14K M14KcTLB M14KcFMM 4KEc 4KEm 4KEp M4K 4Kc 4Km 4Kp 24Kc 24Kf 24KEc 24KEf 34Kc 34Kf 34Kn 74Kc 74Kf 1004Kc 1004Kf 1074Kc 1074Kf microAptivC microAptivP microAptivCF interAptiv interAptivUP proAptiv 5Kf 5Kc 5KEf 5KEc M5100 M5150 M6200 M6250 MIPS32R6 P5600 P6600 I6400 MIPS64R6 I6500 (aliases)
ARM Models    ARM Models aliases ARMv4T ARMv4xM ARMv4 ARMv4TxM ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ ARMv6 ARMv6K ARMv6T2 ARMv6KZ ARMv7 ARM7TDMI ARM7EJ-S ARM720T ARM920T ARM922T ARM926EJ-S ARM940T ARM946E ARM966E ARM968E-S ARM1020E ARM1022E ARM1026EJ-S ARM1136J-S ARM1156T2-S ARM1176JZ-S Cortex-R4 Cortex-R4F Cortex-A5UP Cortex-A5MPx1 Cortex-A5MPx2 Cortex-A5MPx3 Cortex-A5MPx4 Cortex-A8 Cortex-A9UP Cortex-A9MPx1 Cortex-A9MPx2 Cortex-A9MPx3 Cortex-A9MPx4 Cortex-A7UP Cortex-A7MPx1 Cortex-A7MPx2 Cortex-A7MPx3 Cortex-A7MPx4 Cortex-A15UP Cortex-A15MPx1 Cortex-A15MPx2 Cortex-A15MPx3 Cortex-A15MPx4 Cortex-A17MPx1 Cortex-A17MPx2 Cortex-A17MPx3 Cortex-A17MPx4 AArch32 AArch64 Cortex-A53MPx1 Cortex-A53MPx2 Cortex-A53MPx3 Cortex-A53MPx4 Cortex-A57MPx1 Cortex-A57MPx2 Cortex-A57MPx3 Cortex-A57MPx4 Cortex-A72MPx1 Cortex-A72MPx2 Cortex-A72MPx3 Cortex-A72MPx4 MultiCluster ARMv6-M ARMv7-M Cortex-M0 Cortex-M0plus Cortex-M1 Cortex-M3 Cortex-M4 Cortex-M4F (aliases)
POWER Models    POWER Models aliases mpc82x UISA m476 m470 m460 m440 (aliases)
Other Models    Other Models aliases Synopsys ARC_600 Synopsys ARC_605 Synopsys ARC_700 Synopsys ARC_0x21 Synopsys ARC_0x22 Synopsys ARC_0x31 Synopsys ARC_0x32 openCores_generic Andes_N25 Andes_NX25 Microsemi_CoreRISCV SiFive_E31 Xilinx MicroBlaze_V7_00 Xilinx MicroBlaze_V7_10 Xilinx MicroBlaze_V7_20 Xilinx MicroBlaze_V7_30 Xilinx MicroBlaze_V8_00 Xilinx MicroBlaze_V8_10 Xilinx MicroBlaze_V8_20 Xilinx MicroBlaze_V9_50 Xilinx MicroBlaze_V10_00 Xilinx MicroBlaze_ISA Altera Nios II_Nios_II_F Altera Nios II_Nios_II_S Altera Nios II_Nios_II_E (aliases)