|Port Type||Name||Width (bits)||Description|
This page provides detailed information about the OVP Fast Processor Model of the RISC-V RV64I core.
Processor IP owner is RISC-V Foundation.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here. Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas RISC-V RV64I ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The RISC-V RV64I ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.
Model downloadable (needs registration and to be logged in) in package riscv.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.
Model Variant name: RV64I
RISC-V RV64I 64-Bit Family Processor Model.
The Following Instruction Sets are supported
RV32 I - Base Integer Instruction Set
RV64 I - Base Integer Instruction Set
This model only provides an ISA reference implementation, no privilege modes exist for this reference
This Model is released under the Open Source Apache 2.0
This Model is currently work in progress and has many features scheduled, but not yet implemented
Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Extensive testing of supported instructions
This includes tests generated specifically for this model by Imperas
In addition to https://github.com/riscv/riscv-tests
The Model details are based upon the following specifications
---- RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2
---- RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Privileged Architecture Version 1.10
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant RV64I is available OVP_Model_Specific_Information_riscv_RV64I.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: riscv.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.
The RV64I OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_riscv_RV64I.pdf.
Information on the RV64I OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library
http://www.ovpworld.org: Control File User Guide
http://www.ovpworld.org: Using OVP Fast Processor Models with OVPsim and other simulators
http://www.ovpworld.org: PowerPC Bare Metal Video Presentation
http://www.ovpworld.org: Xilinx MicroBlaze Bare Metal Demos Video Presentation
Currently available Fast Processor Model Families.